Many conventional integrated circuits include multiple output terminals for communicating the result of internal calculations or other operations, by way of a data word consisting of multiple binary digits ("bits") presented in parallel. Examples of such circuits include microprocessors and other logic integrated circuits which perform arithmetic computations or logical combinations upon digital data, memory devices which store digital data, interface circuits such as analog-to-digital converters, and other well known classes of integrated circuits. Improvements in the performance of such integrated circuits, particularly the speed at which the circuit can perform its intended function and provide the correct result, are of course desirable and are being achieved in this field.
As is well known in this field, the ability of the output terminals to switch from one logic state to another is a significant factor in the performance of the integrated circuit, especially for those circuits which must drive loads having significant impedance (e.g., TTL loads); the impedance of such loads is generally dominated by resistive and capacitive components. In order to quickly charge up the capacitance of the load, whether the load is another integrated circuit, a transmission line, or both, the integrated circuit must be capable of providing relatively large amounts of current (on the order of milliamperes) over short periods of time (on the order of nanoseconds), in order to meet modern performance requirements.
The integrated circuits, the physical terminals connected thereto, as well as the printed circuit board lines and other conductors to which the integrated circuit terminals are connected, necessarily include parasitic inductance. Due to the presence of the parasitic inductance, together with the large amounts of instantaneous current supplied over short periods of time, noise is generated at the outputs of the integrated circuits having a magnitude equal to the product of the inductance and the rate of change of the current (i.e., dv=Ldi/dt). As the performance of the circuits is enhanced so that the switching times are reduced, for the same load current requirements and the same parasitic inductance, the induced noise at the outputs necessarily increases.
Furthermore, a trend is continuing where integrated circuits such as microprocessors and memories are presenting wider data words, i.e., more bits, at their outputs. Considering the amount of induced noise for switching times of less than five nanoseconds at load specifications which require milliamps of current, and especially considering the simultaneous switching of from eight to thirty-two outputs, the amount of noise generated by modern integrated circuits can be significant in the system environment. Such noise can not only adversely affect the operation of other integrated circuits in the system, for example by causing false data states to be detected, but may also be of sufficient magnitude as to upset the integrated circuit itself cause erroneous internal operation.
To combat the problem of switching noise generated at the outputs of integrated circuits, a prior technique includes series resistors in the output buffer circuits to control the slew rate at which the output drivers turn on and off. Referring to FIG. 1, conventional output buffer circuits 10.sub.0 and 10.sub.1 for driving output terminals D.sub.0 and D.sub.1, respectively, are shown. Output buffer circuits 10.sub.0 and 10.sub.1 receive data input lines IN.sub.0 and IN.sub.1, respectively. Each of output buffer circuits 10.sub.0 and 10.sub.1 also receive output disable line DIS, and inverted output disable line DIS.sub.-- generated by inverter 11 inverting the state of line DIS. Output disable line DIS is generated by control circuitry in the integrated circuit containing output buffers 10, in the conventional manner. Output buffers 10 each will present a high impedance condition at their respective D terminals responsive to line DIS being at a high logic level.
Of course, the number of output terminals D can number as many as thirty-two or sixty-four for a single integrated circuit. For purposes of clarity and ease of description, only the two output buffers 10.sub.0 and 10.sub.1 are shown in FIG. 1 and will be described herein.
Each output buffer 10 includes a push-pull driver for driving its respective output terminal D. In this example, referring to output buffer 10.sub.0 by way of example, a CMOS push-pull driver is used which consists of p-channel pull-up transistor 12.sub.0 with its source connected to V.sub.cc, and n-channel pull-down transistor 14.sub.0 having its source connected to ground. The drains of transistors 12.sub.0 and 14.sub.0 are connected together, and drive the associated output terminal D.sub.0. It should be noted that electrostatic discharge protection devices may be provided between V.sub.cc and terminal D.sub.0, and between ground and terminal D.sub.0, in parallel with transistors 12.sub.0 and 14.sub.0, respectively, in the conventional manner. The gate of pull-up transistor 12.sub.0 is controlled by the output of NAND function 20.sub.0, and the gate of pull-down transistor 14.sub.0 is controlled by the output of NOR function 22.sub.0. The inputs to NAND 20.sub.0 are data input line IN.sub.0 and inverted output disable line DIS.sub.-- ; NOR 22.sub.0 receives data input line IN.sub.0 and output disable line DIS at its inputs.
The construction of NAND 20.sub.0 and of NOR 22.sub.0 in this example of output buffer 10.sub.0 is according to conventional designs for CMOS NAND and NOR functions, as are well known in the art. Accordingly, NAND 20.sub.0 is constructed with p-channel transistors 16 having their source-drain paths connected in parallel with one another between node PNAND.sub.0 and the gate of transistor 12.sub.0 (i.e., the output of NAND 20.sub.0), with one of transistors 16 having its gate connected to data input line IN.sub.0 and the other of transistors 16 having its gate connected to inverted output disable line DIS.sub.--. NAND 20.sub.0 further includes n-channel transistors 18 having their source-drain paths connected in series between node GNAND.sub.0 and the gate of transistor 12.sub.0 ; one of transistors 18 has its gate connected to data input line IN.sub.0 and the other of transistors 18 has its gate connected to inverted output disable line DIS.sub.--. Node PNAND.sub.0 is biased to V.sub.cc through resistor R1.sub.0, and node GNAND.sub.0 is biased to ground through resistor R2.sub.0. Accordingly, NAND 20.sub.0 performs the logical NAND of data input line IN.sub.0 and inverted output disable line DIS.sub.--.
Similarly, NOR 22.sub.0 is constructed as a conventional CMOS two-input NOR gate, with the inputs thereto being data input line IN.sub.0 and disable line DIS. NOR 22.sub.0 includes p-channel transistors 17 having their source-drain paths connected in series between node PNOR.sub.0 and the gate of transistor 17.sub.0 ; one of transistors 17 has its gate connected to data input line IN.sub.0 and the other of transistors 17 has its gate connected to disable line DIS. N-channel transistors 19 have their source-drain paths connected in parallel between node GNOR.sub.0 and the gate of transistor 14.sub.0 ; one of transistors 19 receives data input line IN.sub.0 at its gate, and the other of transistors 19 receives disable line DIS at its gate. Node PNOR.sub.0 is biased to V.sub.cc through resistor R3.sub.0, and node GNOR.sub.0 is biased to ground through resistor R4.sub.0. Accordingly, NOR 22.sub.0 presents the logical NOR of data input line IN.sub.0 and output disable line DIS at its output, to the gate of transistor 14.sub.0.
In operation, when enabled by line DIS being at a low logic level and line DIS.sub.-- being at a high logic level, NAND 20.sub.0 will present the complement of data input line IN.sub.0 to the gate of pull-up transistor 12.sub.0, and NOR 22.sub.0 will present the complement of data input line IN.sub.0 to the gate of pull-down transistor 14.sub.0. Since transistor 12.sub.0 is p-channel, and since transistor 14.sub.0 is n-channel, a high logic level on data input line IN.sub.0 will cause transistor 12.sub.0 to be on and transistor 14.sub.0 to be off, such that a high logic level will appear at terminal D.sub.0. Conversely, a low logic level on data input line IN.sub.0 will cause transistor 12.sub.0 to be off and transistor 14.sub.0 to be on, presenting a low logic level at terminal D.sub.0. If output disable line DIS is at a high logic level (and inverted output disable line DIS.sub.-- thus at a low logic level), both of transistors 12.sub. 0 and 14.sub.0 will be off, presenting a high impedance state at terminal D.sub.0.
Output buffer 10.sub.1 of FIG. 1 is, of course, constructed similarly as output buffer 10.sub.0. Output buffer 10.sub.1 operates in a similar manner to present a data state at terminal D.sub.1 according to the data state of data input line IN.sub.1, when enabled, and to present a high impedance state thereat responsive to output disable line DIS being at a high logic level. For ease of illustration, NAND function 20.sub.1 and NOR function 22.sub.1 are shown in FIG. 2 in conventional logic gate form; however, as shown in FIG. 2, NAND 22.sub.1 is biased through its associated resistors R1.sub.1 and R2.sub.1, and NOR 22.sub.1 is biased through its associated resistors R3.sub.1 and R4.sub.1.
The purpose of resistors R1 through R4 for each of output buffers 10 in the conventional arrangement of FIG. 1 is for purposes of controlling the switching rate of output buffers 10, and limiting the noise generated at the output terminals D. Referring to NAND 20.sub.0 for example, the speed at which either of p-channel transistors 16 can pull up the gate of transistor 12.sub.0 toward V.sub.cc (responsive to either of data input lines IN.sub.0 or inverted output disable line DIS.sub.-- being low) will decrease with larger values of resistance for resistor R1.sub.0, and will increase with smaller values of resistance for resistor R1.sub.0. Similarly, the speed at which n-channel transistors 18 can discharge the gate of transistor 12.sub.0 to ground (responsive to both of data input lines IN.sub.0 and inverted output disable line DIS.sub.-- being high) will decrease with larger resistance values of resistor R2.sub.0 and increase with smaller resistance values for resistor R2.sub.0.
Accordingly, in this conventional arrangement, the resistance values of resistors R1 through R4 can be selected, for each of output buffers 10, to control the speed at which terminals D switch state, and thus control the Ldi/dt noise generated thereby. A further benefit of reducing the switching speed of the NANDs 20 and NORs 22 is that crowbar current through the push-pull transistors 12 and 14 can be avoided, for example by selecting the resistor values R1 through R4 so that each of the transistors 12 and 14 turn on slowly, but turn off quickly. To achieve this, resistors R1 and R4 would have relatively low resistance, and that resistors R2 and R3 would have relatively high resistance. This control of the Ldi/dt noise, and minimization of crowbar current by use of resistors R1 through R4 will, of course, require trade-off with reduced switching speed of output terminals D. Selection of the resistor values have been made, according to these parameters, by circuit designers in the art.
This conventional configuration of output buffers 10 as shown in FIG. 1 requires four resistors R1 through R4 for each output buffer 10. For those devices which have eight or more output terminals, thirty-two resistors are thus required. In the manufacture of modern integrated circuits, resistors which are formed in polysilicon or in diffused regions can consume significant chip area. This is especially the case where the material which is preferred for the resistors, for example polysilicon, has relatively high conductivity. Accordingly, in the conventional configuration of FIG. 1, either significant chip surface area is consumed to provide resistors R1 through R4 for each output buffer 10, or the manufacturing process must be made significantly more complex in order to provide material of the appropriate low conductivity so that resistors R1 through R4 for each output buffer 10 can be realized in reduced chip area.
It is therefore an object of this invention to provide a output buffer circuit which provides reduced noise at the outputs for multiple output buffers in reduced chip area from that of the prior art.
It is a further object of this invention to provide such a circuit incorporating resistors having improved matching with transistors in the integrated circuit.
It is a further object of this invention to provide such a circuit where the resistor material is of relatively high conductivity.
It is a further object of this invention to provide such a circuit where the current through the resistors is limited, for improved reliability.
It is a further object of this invention to provide such a circuit having selectable resistance values to allow minimizing output switching noise based on circuit speed.